The present invention relates to techniques for controlling on-chip termination resistance, and more particularly, to techniques for precision biasing output drivers for controlling an on-chip termination resistance.
When transmitting signals over distances that are appreciable with respect to the signal period, mismatches between the impedance of the transmission line and that of the receiver cause signal reflection. The reflected signal interferes with the transmitted signal and causes distortion and degrades the overall signal integrity. To minimize or eliminate the unwanted reflection, transmission lines are resistively terminated by a matching impedance. In the case of integrated circuits that are in communication with other circuitry on a circuit board, termination is often accomplished by coupling an external termination resistor to the relevant input/output (I/O) pins.
For many of today's high speed integrated circuits, and particularly those that have large I/O pin counts, external termination poses a number of problems. A termination resistor is typically coupled to every I/O pin receiving an input signal from a transmission line. Often hundreds of termination resistors are needed for an integrated circuit. Numerous external termination resistors can consume a substantial amount of board space. The use of external components for termination purposes can be cumbersome and costly, especially in the case of an integrated circuit with numerous I/O pins.
Signal integrity is critical in digital design as system speeds and clock edge rates continue to increase. To improve signal integrity, both single-ended and differential signals should be properly terminated. Termination can be implemented with external termination resistors on a board or with on-chip termination technology. On-chip termination eliminates the need for external resistors and simplifies the design of a circuit board.
There is some degree of flexibility provided by circuits such as field programmable gate arrays (FPGAs) wherein a user may be provided the option of programmable changing the output driver settings. To reduce die size, an FPGA design may be converted to a structured application specific integrated circuit (ASIC) using a mask field programmable gate array (MFPGA) that fixes the switch settings. This conversion which removes the programmability of the switches and routing become economically desirable at higher volumes. In a structured ASIC design, therefore, the user may loses the option to change the output driver settings. The output drive strength is set according to the user's FPGA design, and the setting is hardwired in the structured ASIC.
A circuit designer can map a user's I/O drive strength settings from an FPGA to a structured ASIC through simulation or test chip correlation. However, process, voltage, and temperature (PVT) variations and other parasitic effects can complicate the mapping effort. Therefore, such a mapping process is not desirable, because the FPGA-to-structured ASIC conversion process typically has a short turn-around time.
One of the objectives when converting an FPGA design into a structured ASIC design is to reduce the die size and the chip production cost. One way to reduce die size is to reduce the number of user drive strength options in the I/O drivers of the structured ASIC design. However, removing user drive strength options compromises the I/O drive strength resolution. As a result, the user may have to settle for a drive strength setting that is different from the FPGA. The user typically wants to keep the same drive strength setting so that the structured ASIC can interface with neighboring chips with the same drive strength settings used in the FPGA.
It would therefore be desirable to implement termination resistance on-chip to reduce the number of external components. It would also be desirable to provide accurate control of an on-chip termination resistance. It would further be desirable to provide the user with the flexibility to adjust the drive strength setting of an I/O driver in a structured ASIC.